View HY5PS1G831CFP-Y5_2267267.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this document is a general product descript ion and is subject to change without notic e. hynix semiconductor does not assume any responsibility for use of circuits descr ibed. no patent licenses are implied. rev. 0.2 / dec 2006 1 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 1gb ddr2 sdram hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp
rev. 0.2 /dec 2006 2 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp revision details rev. history draft date 0.1 initial data sheet released nov. 2006 0.2 idd values added dec. 2006
rev. 0.2 / dec 2006 3 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp contents 1. description 1.1 device features and ordering information 1.1.1 key ?????? 1.1.2 ordering information 1.1.3 ordering frequency 1.2 pin configuration 1.3 pin description 2. maximum dc ratings 2.1 absolute maximum dc ratings 2.2 operating temperature condition 3. ac & dc oper ating conditions 3.1 dc operating conditions 5.1.1 recommended dc operating conditions(sstl_1.8) 5.1.2 odt dc electrical characteristics 3.2 dc & ac logic input levels 3.2.1 input dc logic level 3.2.2 input ac logic level 3.2.3 ac input test conditions 3.2.4 differential input ac logic level 3.2.5 differential ac output parameters 3.3 output buffer levels 3.3.1 output ac test conditions 3.3.2 output dc current drive 3.3.3 ocd default ???????????? 3.4 idd specifications & measurement conditions 3.5 input/output capacitance 4. ac timing specifications 5. package dimensions
rev. 0.2 /dec 2006 4 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 1.1 device features & ordering information 1.1.1 key features ? vdd = 1.8v +/- 0.1v ? vddq = 1.8v +/- 0.1v ? all inputs and outputs are compatible with sstl_18 interface ?8 banks ? fully differential clock inputs (ck, /ck) operation ? double data rate interface ? source synchronous-data transaction aligne d to bidirectional da ta strobe (dqs, dqs ) ? differential data strobe (dqs, dqs ) ? data outputs on dqs, dqs edges when read (edged dq) ? data inputs on dqs centers when write(centered dq) ? on chip dll align dq, dqs and dqs transition with ck transition ? dm mask write data-in at the both risi ng and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and da ta masks latched on the rising edges of the clock ? programmable cas latency 3, 4, 5 and 6 supported ? programmable additive latency 0, 1, 2, 3, 4 and 5 supported ? programmable burst length 4/8 with both nibble sequential and interleave mode ? internal eight bank operations with single pulsed ras ? auto refresh and self refresh supported ? tras lockout supported ? 8k refresh cycles /64ms ? jedec standard 60ball fbga(x4/x8) , 84ball fbga(x16) ? full strength driver option controlled by emrs ? on die termination supported ? off chip driver impedance adjustment supported ? read data strobe supported (x8 only) ? self-refresh high temperature entry ordering information part no. configuration package hy5ps1g431c(l)fp-xx* 256mx4 60 ball hy5ps1g831c(l)fp-xx* 128mx8 hy5ps1g1631c(l)fp-xx* 64mx16 84 ball operating frequency grade tck(ns) cl trcd trp unit e3 5333 clk c4 3.75 4 4 4 clk y5 3555 clk s5 2.5 5 5 5 clk note: -xx* is the speed bin, refer to the operation frequency table for complete part no. 1. description
rev. 0.2 /dec 2006 5 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 1.2 pin configuration & address table 256mx4 ddr2 pin configuration (top view: see balls through package) row and column address table items 256mx4 # of bank 8 bank address ba0,ba1,ba2 auto precharge flag a10/ap row address a0 - a13 column address a0-a9, a11 page size 1 kb vss dm vddq dq3 vss we ba1 a1 a5 a9 nc nc vssq dq1 vssq vref cke ba0 a10 a3 a7 a12 vdd nc vddq nc vddl ba2 vss vdd a b c d e f g h j k vssq dqs vddq dq2 vssdl ras cas a2 a6 a11 nc dqs vssq dq0 vssq ck ck cs a0 a4 a8 a13 vddq nc vddq nc vdd odt vdd vss l 3 2 1 78 9
rev. 0.2 /dec 2006 6 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 128mx8 ddr2 pin configuration (top view: see balls through package) row and column address table items 128mx8 # of bank 8 bank address ba0, ba1, ba2 auto precharge flag a10/ap row address a0 - a13 column address a0-a9 page size 1 kb vss dm/rdqs vddq dq3 vss we ba1 a1 a5 a9 nc nu/rdqs vssq dq1 vssq vref cke ba0 a10 a3 a7 a12 vdd dq6 vddq dq4 vddl ba2 vss vdd a b c d e f g h j k vssq dqs vddq dq2 vssdl ras cas a2 a6 a11 nc dqs vssq dq0 vssq ck ck cs a0 a4 a8 a13 vddq dq7 vddq dq5 vdd odt vdd vss l 3 2 1 78 9
rev. 0.2 /dec 2006 7 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 64mx16 ddr2 pin configuration (top view: see balls through package) row and column address table items 64mx16 # of bank 8 bank address ba0, ba1, ba2 auto precharge flag a10/ap row address a0 - a12 column address a0-a9 page size 2 kb 3 vss udm vddq dq11 vss we ba1 a1 a5 a9 nc, a14 2 nc vssq dq9 vssq vref cke ba0 a10/ap a3 a7 a12 1 vdd dq14 vddq dq12 vddl nc, ba2 vss vdd a f g h j k l m 7 vssq udqs vddq dq10 vssdl ras cas a2 a6 a11 nc, a15 8 udqs vssq dq8 vssq ck ck cs a0 a4 a8 nc, a13 9 vddq dq15 vddq dq13 vdd odt vdd vss vss ldm vddq dq3 nc vssq dq1 vssq vdd dq6 vddq dq4 b c d e vssq ldqs vddq dq2 ldqs vssq dq0 vssq vddq dq7 vddq dq5 n p r
rev. 0.2 /dec 2006 8 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp idd test conditions (idd values are for full operating range of voltage and temperature, notes 1-5) symbol conditions units idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t ras min(idd) ; cke is high, cs is high between valid commands;address bus inputs are switching;data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd) ; cke is high, cs is high between valid commands ; address bus inputs are switching ; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle ; t ck = t ck(idd) ; cke is low ; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ;all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs ar e switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burs t reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inpu ts are switching;; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other co ntrol and address bus inputs are switch- ing; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid comma nds; address bus inputs are stable during deselects; data pattern is same as idd4r; - refer to the following page for detailed timing conditions ma
rev. 0.2 /dec 2006 9 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp note: 1. vddq = 1.8 +/- 0.1v ; vdd = 1.8 +/- 0.1v (exclusively vddq = 1.9 +/- 0.1v ; v dd = 1.9 +/- 0.1v for c3 speed grade) 2. idd specifications are tested after the device is properly initialized 3. input slew rate is specified by ac parametric test condition 4. idd parameters are specified with odt disabled. 5. data bus consists of dq, dm, dqs, dqs, rdqs, rdqs , ldqs, ldqs, udqs, and udqs. idd values must be met with all combinations of emrs bits 10 and 11. 6. definitions for idd low is defined as vin vilac(max) high is defined as vin ? vihac(min) stable is defined as inputs stable at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals, and in puts changing between high and low every other data transfer (once per clock)for dq signals not including masks or strobes.
rev. 0.2 /dec 2006 10 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 2. maximum dc ratings 2.1 absolute maxi mum dc ratings note: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the device at these or any other conditions above those indicated in the operational sectio ns of this specification is not implie d. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the ????? /top side of the dram. for the measurement conditions. please refer to jesd51-2 standard. 2.2 operating temperature condition note: 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measure- ment conditions, please refer to jesd51-2 standard. 2. at 85~95 t oper , double refresh rate(trefi: 3.9us) is required, and to enter the self refresh mode at this tem- perature range, an emrs command is required to change nternal refresh rate. symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 1.0 v ~ 2.3 v v 1 vddq voltage on vddq pin relative to vss - 0.5 v ~ 2.3 v v 1 vddl voltage on vddl pin relative to vss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to vss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1, 2 i i input leakage current; any input 0v vin vdd; all other balls not under test = 0v) -2 ua ~ 2 ua ua i oz output leakage current; 0v vout vddq; dq and odt disabled -5 ua ~ 5 ua ua symbol parameter rating units notes t oper operating temperature 0 to 95 c 1,2
rev. 0.2 /dec 2006 11 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 3. ac & dc operating conditions 3.1 dc operating conditions 3.1.1 recommended dc operating conditions (sstl_1.8) note: 1. min. typ. and max. values increase by 100mv for c3(ddr2-533 3-3-3) speed option. 2. vddq tracks with vdd,vddl tracks with vdd. ac parameters are measured with vdd,vddq and vdd. 3. the value of vref may be selected by the user to pr ovide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 x vddq of the transmitting device and vref is expected to track varia- tions in vddq 4. peak to peak ac noise on vref may not exceed +/-2% vref (dc). 5. vtt of transmitting device must track vref of receiving device. 3.1.2 odt dc electrical characteristics note : 1. test condition for rtt measurements measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin separately, then measure current i(v ih (ac)) and i(v il (ac)) respectively. v ih (ac), v il (ac), and vddq values defined in sstl_18 measurement definition for vm : measurement vo ltage at test pin(mid point) with no load. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v 1 vddl supply voltage for dll 1.7 1.8 1.9 v 1,2 vddq supply voltage for output 1.7 1.8 1.9 v 1,2 vref input reference voltage 0.49*vddq 0.50*vddq 0.51*vddq mv 3,4 vtt termination voltage vref-0.04 vref vref+0.04 v 5 parameter/condition symbol min nom max units notes rtt effective impedance value for emrs(a6,a2)=0,1; 75 ohm rtt1(eff) 60 75 90 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,0; 150 ohm rtt2(eff) 120 150 180 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,1; 50 ohm rtt3(eff) 40 50 60 ohm 1 deviation of vm with respect to vddq/2 delta vm -6 +6 % 1 rtt(eff) = v ih (ac) - v il (ac) i(v ih (ac)) - i(v il (ac)) delta vm = 2 x vm vddq x 100% - 1
rev. 0.2 /dec 2006 12 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 3.2 dc & ac logic input levels 3.2.1 input dc logic level 3.2.2 input ac logic level 3.2.3 ac input test conditions note: 1. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih(ac) min for rising edges and the range from v ref to v il(ac) max for falling edges as shown in the figure below. 3. ac timings are referenced with input waveforms switchin g from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. < figure : ac input test signal waveform> symbol parameter min. max. units notes v ih (dc) dc input logic high vref + 0.125 vddq + 0.3 v v il (dc) dc input logic low - 0.3 vref - 0.125 v symbol parameter ddr2 400,533 ddr2 667,800 units notes min. max. min. max. v ih (ac) ac input logic high vref + 0.250 - vref + 0.200 - v v il (ac) ac input logic low - vref - 0.250 - vref - 0.200 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih(ac) min v ref v swing(max) delta tr delta tf v ih(dc) min v il(dc) max v il(ac) max v ss rising slew = delta tr v ih(ac) min - v ref v ref - v il(ac) max delta tf falling slew =
rev. 0.2 /dec 2006 13 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 3.2.4 differential input ac logic level note: 1. vin(dc) specifies the allowable dc execution of each input of differential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs and udqs . 2. vid(dc) specifies the input differential voltage |vtr -vcp | required for switching, where vtr is the true input (such as ck, dqs, ldqs or udqs) level and vcp is the complementary input (such as ck , dqs , ldqs or udqs ) level. the minimum value is equa l to vih(dc) - v il(dc). note: 1. vid(ac) specifies the input differential voltage |vtr -vcp | required for switching, where vtr is the true input sig- nal (such as ck, dqs, ldqs or udqs) and vcp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih(ac) - v il(ac). 2. the typical value of vix(ac) is expected to be about 0.5 * vddq of the transmitting device and vix(ac) is expected to track variations in vddq. vix(ac) indicates th e voltage at which differenti al input signals must cross. 3.2.5 differential ac output parameters note: 1. the typical value of vox(ac) is expected to be about 0.5 * v ddq of the transmitting device and vox(ac) is expected to track variations in vd dq. vox(ac) indicates the voltage at ???? differential output signals must cross. symbol parameter min. max. units notes v id (ac) ac differential input voltage 0.5 vddq + 0.6 v 1 v ix (ac) ac differential cross point voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 2 symbol parameter min. max. units notes v ox (ac) ac differential cross point voltage 0.5 * vddq - 0.125 0.5 * vddq + 0.125 v 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels >
rev. 0.2 /dec 2006 14 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 3.3 output buffer characteristics 3.3.1 output ac test conditions note: 1. the vddq of the device under test is referenced. 3.3.2 output dc current drive note: 1. v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh(dc) and i ol(dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating point (see section 3.3) along a 21 oh m load line to define a convenient driver current for measurement. symbol parameter sstl_18 class ii units notes v otr output timing measurement reference level 0.5 * v ddq v1 symbol parameter sstl_18 units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4
rev. 0.2 /dec 2006 15 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 3.3.3 ocd default characteristics note : 1. absolute specifications ( toper; vdd = +1.8v 0.1v, vddq = +1.8v 0.1v) 2. impedance measurement condition for output source dc current: vddq=1.7v; vout=1420mv; (vout- vddq)/ioh must be less than 23.4 ohms for values of vout between vddq and vddq-280mv. impedance measurement condition for output sink dc cu rrent: vddq = 1.7v; vout = 280mv; vout/iol must be less than 23.4 ohms for values of vout between 0v and 280mv. 3. mismatch is absolute value between pull-up and pull-d n, both are measured at same temperature and voltage. 4. slew rate measured from vil(ac) to vih(ac). 5. the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaranteed by design and characterization. 6. this represents the step size when the ocd is ne ar 18 ohms at nominal conditions across all process corners/variations and represents only the dram uncertaint y. a 0 ohm value(no calibration) can only be achieved if the ocd impedance is 18 ohms +/- 0.75 ohms under nominal conditions. output slew rate load: 7. dram output slew rate specification a pplies to 400, 533 and 667 mt/s speed bins. 8. timing skew due to dram output slew rate mis-match between dqs / dqs and associated dqs is included in tdqsq and tqhs specification. description parameter min nom max unit notes output impedance - - - ohms 1 output impedance step size for ocd calibration 0 1.5 ohms 6 pull-up and pull-down mismatch 0 4 ohms 1,2,3 output slew rate sout 1.5 - 5 v/ns 1,4,5,6,7,8 vtt 25 ohms output (vout) reference point
rev. 0.2 /dec 2006 16 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp idd specifications(max) symbol ddr2 400 ddr2 533 ddr2 667 ddr2 800 units x4 x8 x4 x8 x16 x4 x8 x16 x4 x8 x16 idd0 60 60 65 65 85 70 70 90 75 75 95 ma idd1 70 70 75 75 110 80 80 115 85 85 120 ma idd2p 88888888888ma idd2q 22 22 27 27 27 30 30 30 32 32 32 ma idd2n 30 30 35 35 35 40 40 40 45 45 45 ma idd3p f 20 20 20 20 20 25 25 25 25 25 25 ma s 99999999999ma idd3n 35 35 45 45 45 50 50 50 55 55 55 ma idd4w 100 100 125 125 160 150 150 195 170 170 225 ma idd4r 100 100 125 125 160 150 150 195 170 170 225 ma idd5 165 165 165 165 165 175 175 175 175 175 175 ma idd6 normal 88888888888ma low power 55555555555ma idd7 165 165 175 175 260 180 180 265 185 185 270 ma 3.4 idd specifications & test conditions
rev. 0.2 /dec 2006 17 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp idd test conditions (idd values are for full operating range of voltage and temperature, notes 1-5) symbol conditions units idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t ras min(idd) ; cke is high, cs is high between valid commands; address bus inputs are switch- ing;data bus inputs are switching ma idd1 operating one bank active-read-precharge ?????? ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd) ; cke is high, cs is high between valid commands ; address bus inputs are switching ; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle ; t ck = t ck(idd) ; cke is low ; other control and address bus inputs are stable ; data bus inputs are floating ma idd2q precharge quiet standby current ;all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs ar e stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are swit ching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are sw itching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inpu ts are switching;; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other co ntrol and address bus inputs are switch- ing; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating ma floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between hi gh and low every other clock cycle (once per two clocks) for address and control signals, and inputs changing between high and low every other data transfer (once per clock) for dq signals no t including masks or strobes. idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; - refer to the following page for detailed timing conditions ma
rev. 0.2 /dec 2006 18 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp note : 1. vddq = 1.8 +/- 0.1v ; vdd = 1.8 +/- 0.1v (exclusively vddq = 1.9 +/- 0.1v ; vdd = 1.9 +/- 0.1v for c3 speed grade) 2. idd specifications are tested after the device is properly initialized 3. input slew rate is specified by ac parametric test condition 4. idd parameters are specified with odt disabled. 5. data bus consists of dq, dm, dqs, dqs, rdqs, rdqs , ldqs, ldqs, udqs, and udqs. idd values must be met with all combinations of emrs bits 10 and 11. 6. definitions for idd low is defined as vin vilac(max) high is defined as vin ? vihac(min) stable is defined as inputs stable at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals, and in puts changing between high and low every other data transfer (once per clock) for dq signals not including masks or strobes.
rev. 0.2 /dec 2006 19 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp for purposes of idd testing, the follo wing parameters are to be utilized detailed idd7 the detailed timings are shown below for idd7. changes will be required if timi ng parameter changes are made to the specification. legend: a = active; ra = read with autoprecharge; d = deselect idd7: operating current: all bank interleave read operation all banks are being interleaved at minimum t rc(idd) without violating t rrd(idd) using a burst length of 4. control and address bus inputs are stable during deselects. iout = 0ma timing patterns for 4 bank devices x4/ x8/ x16 -ddr2-400 4/4/4: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d d -ddr2-400 3/3/3: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d -ddr2-533 5/4/4: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d -ddr2-533 4/4/4: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d timing patterns for 8 bank devices x4/8 -ddr2-400 all bins: a0 ra0 a1 ra1 a2 ra2 a3 ra3 a4 ra4 a5 ra5 a6 ra6 a7 ra7 -ddr2-533 all bins: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d timing patterns for 8 bank devices x16 -ddr2-400 all bins: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d -ddr2-533 all bins: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d a4 ra4 d a5 d a6 ra6 d a7 ra7 d d d ddr2-800 ddr2- 667 ddr2- 533 ddr2- 400 parameter 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 units cl(idd) 56543tck t rcd(idd) 12.515151515 ns t rc(idd) 57.5 60 60 60 55 ns t rrd(idd)-x4/x8 7.5 7.5 7.5 7.5 7.5 ns t rrd(idd)-x16 10 10 10 10 10 ns t ck(idd) 2.5 2.5 3 3.75 5 ns t rasmin(idd) 45 45 45 45 40 ns t rasmax(idd) 70000 70000 70000 70000 70000 ns t rp(idd) 12.515151515ns t rfc(idd)-256mb 75 75 75 75 75 ns t rfc(idd)-512mb 105 105 105 105 105 ns t rfc(idd)-1gb 127.5 127.5 127.5 127.5 127.5 ns t rfc(idd)-2gb 197.5 197.5 197.5 197.5 197.5 ns
rev. 0.2 /dec 2006 20 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 3.5. input/output capacitance 4. electrical characteristics & ac timing specification ( 0 ? ? ? ? t case ? ? 95? ?; v ddq = 1.8 v +/- 0.1v; v dd = 1.8v +/- 0.1v) refresh parameters by device density ddr2 sdram speed bins and trcd, trp and trc for corresponding bin note 1 : 8 bank device precharge all allowance : trp for a prec harge all command for an 8 bank device will equal to trp+1*tck, where trp are the values for a single bank ?????? , which are shown in the table above. parameter symbol ddr2 400 ddr2 533 ddr2 667 ddr2 800 units min max min max input capacitance, ck and ck cck 1.0 2.0 1.0 2.0 pf input capacitance delta, ck and ck cdck x 0.25 x 0.25 pf input capacitance, all other input-only pins ci 1.0 2.0 1.0 2.0 pf input capacitance delta, all other input-only pins cdi x 0.25 x 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 4.0 2.5 3.5 pf input/output capacitance delta, dq, dm, dqs, dqs cdio x 0.5 x 0.5 pf parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/refresh command time trfc 75 105 127.5 195 327.5 ns average periodic refresh interval trefi 0 ? ?? ? t case ? ? 95? ? 7.8 7.8 7.8 7.8 7.8 ns 85 ? ? t case ? ? 95? ? 3.9 3.9 3.9 3.9 3.9 ns speed ddr2-800 ddr2-667 ddr2-533 ddr2-400 units bin(cl-trcd-trp) 5-5-5 6-6-6 4-4-4 5-5-5 4-4-4 3-3-3 parameter min min min min min min cas latency 564543tck trcd 12.5 15 12 15 15 15 ns trp note1 12.5 15 12 15 15 15 ns tras 45 45 45 45 45 40 ns trc 57.5 60 57 60 60 55 ns
rev. 0.2 /dec 2006 21 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp timing parameters by speed grade parameter symbol ddr2-400 ddr2-533 unit note min max min max dq output access time from ck/ck tac -600 +600 -500 +500 ps dqs output access time from ck/ck tdqsck -500 +500 -450 +450 ps ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl, tch) - min(tcl, tch) - ps 11,12 clock cycle time, cl=x tck 5000 8000 3750 8000 ps 15 dq and dm input setup time(differential strobe) tds(base) 150 - 100 - ps 6,7,8,20 dq and dm input hold time(differential strobe) tdh(base) 275 - 225 - ps 6,7,8,21 dq and dm input setup time(single ended strobe) tds 25 --25 - ps 6,7,8,20 dq and dm input hold time(single ended strobe) tdh 25 --25 - ps 6,7,8,21 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse width for each input tdipw 0.35 - 0.35 - tck data-out high-impedance time from ck/ck thz - tac max - tac max ps 18 dqs low-impedance time from ck/ck tlz (dqs) tac min tac max tac min tac max ps 18 dq low-impedance time from ck/ck tlz (dq) 2*tac min tac max 2*tac min tac max ps 18 dqs-dq skew for dqs and associated dq signals tdqsq - 350 - 300 ps 13 dq hold skew factor tqhs - 450 - 400 ps 12 dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps write command to first dqs latching transition tdqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck 10 write preamble twpre 0.35 - 0.35 - tck address and control input setup time tis 350 - 250 - ps 5,7,9,23 address and control input hold time tih 475 - 375 - ps 5,7,9,23 read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck active to active command period for 1kb page size products (x4, x8) trrd 7.5 -7.5 - ns 4 active to active command period for 2kb page size products (x16) trrd 10 -10 - ns 4
rev. 0.2 /dec 2006 22 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp parameter symbol ddr2-400 ddr2-533 uni t note min max min max four active window for 1kb page size products tfaw 37.5 -37.5 - ns four active window for 2kb page size products tfaw 50 -50 - cas to cas command delay tccd 2 2 tck write recovery time twr 15 -15 - ns auto precharge write recovery + precharge time tdal wr+trp* - wr+trp* - tck 14 internal write to read command delay twtr 10 -7.5 - ns 24 internal read to precharge command delay trtp 7.5 7.5 ns 3 exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - tck exit active power down to read command txard 2 2 tck 1 exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al tck 1, 2 cke minimum pulse width (high and low pulse width) t cke 3 3 tck odt turn-on delay t aond 2222tck odt turn-on t aon tac(min) tac(max) +1 tac(min) tac(max) +1 ns 16 odt turn-on(power-down mode) t aonp d tac(min)+ 2 2tck+tac (max) +1 tac(min)+ 2 2tck+tac (max)+1 ns odt turn-off delay t aofd 2.5 2.5 2.5 2.5 tck odt turn-off t aof tac(min) tac(max) + 0.6 tac(min) tac(max) + 0.6 ns 17 odt turn-off (power-down mode) t aofpd tac(min)+ 2 2.5tck+ta c(max)+1 tac(min)+ 2 2.5tck+t ac(max) +1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+ti h tis+tck+ti h ns 15 -continued
rev. 0.2 /dec 2006 23 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp parameter symbol ddr2-667 ddr2-800 unit note min max min max dq output access time from ck/ck tac -450 +450 -400 +400 ps dqs output access time from ck/ck tdqsck -400 +400 -350 +350 ps ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl, tch) - min(tcl, tch) - ps 11,12 clock cycle time, cl=x tck 3000 8000 2500 ps 15 dq and dm input setup time tds(base) 100 - 50 - ps 6,7,8,20 dq and dm input hold time tdh(base) 175 - 125 - ps 6,7,8,21 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse width for each input tdipw 0.35 - 0.35 - tck data-out high-impedance time from ck/ck thz - tac max - tac max ps 18 dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps 18 dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max ps 18 dqs-dq skew for dqs and associated dq signals tdqsq - 240 -200 ps 13 dq hold skew factor tqhs - 340 -300 ps 12 dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps first dqs latching transition to associated clock edge tdqss - 0.25 + 0.25 - 0.25 + 0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck 10 write preamble twpre 0.35 - 0.35 - tck address and control input setup time tis(base) 200 -175 - ps 5,7,9,22 address and control input hold time tih(base) 275 -250 - ps 5,7,9,23 read preamble trpre 0.9 1.1 0.9 1.1 tck 19 read postamble trpst 0.4 0.6 0.4 0.6 tck 19 activate to precharge command tras 45 70000 45 70000 ns 3 active to active command period for 1kb page size products (x4, x8) trrd 7.5 -7.5 - ns 4 active to active command period for 2kb page size products (x16) trrd 10 -10 - ns 4 four active window for 1kb page size products tfaw 37.5 - 37.5 - ns four active window for 2kb page size products tfaw 50 - 50 - ns cas to cas command delay tccd 2 2 tck write recovery time twr 15 -15 - ns auto precharge write recovery + precharge time tdal wr+trp - wr+trp - tck 14
rev. 0.2 /dec 2006 24 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp -continue- parameter symbol ddr2-667 ddr2-800 unit note min max min max internal write to read command delay twtr 7.5 -7.5 - ns internal read to precharge command delay trtp 7.5 7.5 ns 3 exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - tck exit active power down to read command txard 2 2 tck 1 exit active power down to read command (slow exit, lower power) txards 7 - al 8 - al tck 1, 2 cke minimum pulse width (high and low pulse width) t cke 3 3 tck odt turn-on delay t aond 2222tck odt turn-on t aon tac(min) tac(max) +0.7 tac(min) tac(max) +0.7 ns 6,16 odt turn-on(power-down mode) t aonpd tac(min)+2 2tck+ tac(max)+1 tac(min) +2 2tck+ tac(max)+1 ns odt turn-off delay t aofd 2.5 2.5 2.5 2.5 tck odt turn-off t aof tac(min) tac(max)+ 0.6 tac(min) tac(max) +0.6 ns 17 odt turn-off (power-down mode) t aofpd tac(min) +2 2.5tck+ tac(max)+1 tac(min) +2 2.5tck+ tac(max)+1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+tih tis+tck +tih ns 15
rev. 0.2 /dec 2006 25 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp general notes, which may ap ply for all ac parameters 1. slew rate measurement levels a. output slew rate for falling and rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals. for differ ential signals (e.g. dqs - dqs ) output slew rate is measured between dqs - dqs = -500 mv and dqs - dqs = +500mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. b. input slew rate for single ended signals is measur ed from dc-level to ac-level: from vref - 125 mv to vref + 250 mv for rising edges and from vref + 125 mv and vref - 250 mv for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = -250 mv to ck - ck = +500 mv (250mv to -500 mv for falling egdes). c. vid is the magnitude of the difference between the input voltage on ck and the input voltage on ck , or between dqs and dqs for differential strobe. 2. ddr2 sdram ac timing reference load the following figure represents the timing reference l oad used in defining the relevant timing parameters of the part. it is not intended to be either a precis e representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simula- tion tools to correlate the timing reference load to a sy stem environment. manufacturers will correlate to their production test conditions (generally a coaxial tran smission line terminated at the tester electronics). the output timing reference voltage level for single ende d signals is the crosspoint with vtt. the output tim- ing reference voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs) signal. 3. ddr2 sdram output slew rate test load output slew rate is characterized under the test conditions as shown below. vddq dut dq dqs dqs rdqs rdqs output v tt = v ddq /2 25 timing reference point ac timing reference load vddq dut dq dqs, dqs rdqs, rdqs output v tt = v ddq /2 25 test point slew rate test load
rev. 0.2 /dec 2006 26 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 4. differential data strobe ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the emrs ?enable dqs? mode bit; timing ad vantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timi ngs are measured is mode dependent. in single vref. in differential mode, these timing relationships ar e measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is guarante ed by design and charac terization. note that when differential data strobe mode is disabled via the em rs, the complementary pin, dqs , must be tied externally to vss through a 20 ohm to 10 k ohm resistor to insure proper operation. 5. ac timings are for linear signal transitions. see system derating for other signal transitions. 6. these parameters guarantee device behavior, but th ey are not necessarily tested on each device. they may be guaranteed by device design or tester correlation. 7. all voltages referenced to vss. 8. tests for ac timing, idd, and electrical (ac and dc) characteristics, may be conducted at nominal refer- ence/supply voltage levels, but the related specificatio ns and device operation are guaranteed for the full voltage range specified. t ds t ds t dh t wpre t wpst t dqsh t dqsl dqs dqs d dmin dqs/ dq dm t dh figure -- data input (write) timing dmin dmin dmin d d d dqs v ih (ac) v il (ac) v ih (ac) v il (ac) v ih (dc) v il (dc) v ih (dc) v il (dc) t ch t cl ck ck ck/ck dqs/dqs dq dqs dqs t rpst q t rpre t dqsqmax t qh t qh t dqsqmax figure -- data output (read) timing q qq
rev. 0.2 /dec 2006 27 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp specific notes for de dicated ac parameters 1. user can choose which active power down exit timi ng to use via mrs(bit 12). txard is expected to be used for fast active power down exit timing. txards is expected to be us ed for slow active power down exit timing where a lower power value is defined by each vendor data sheet. 2. al = additive latency 3. this is a minimum requirement. minimum read to pr echarge timing is al + bl/2 providing the trtp and tras(min) have been satisfied. 4. a minimum of two clocks (2 * tck) is re quired irrespective of operating frequency 5. timings are guaranteed with comma nd/address input slew rate of 1.0 v/ns. see system derating for other slew rate values. 6. timings are guaranteed with data, mask, and (dqs/r dqs in singled ended mode) input slew rate of 1.0 v/ns. see system derating for other slew rate values. 7. timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. timings are guaranteed for dqs sig- nals with a differential slew rate of 2.0 v/ns in differ ential strobe mode and a slew rate of 1v/ns in single ended mode. see system derating for other slew rate values. 8. tds and tdh derating 1) for all input signals the total tds(setup time) and tdh(hold ti me) required is calculated by adding the datasheet value to t he derating value listed in table x. setup(tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the firs t crossing of vih(ac)min. setup(tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref( dc) and the first crossing of vil(ac)max. if the actual signal is al ways earlier than the nominal slew rate line between shaded ? vref(dc) to ac region?, use nominal slew rate for derating value(see fig a.) if the actual signal is later than the nominal slew rate line anywhere bet ween shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for deratin g value(see fig b.) hold(tdh) nominal slew rate for a risi ng signal is defined as the slew ?? between the last crossing of vil(dc) max and the first crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc) min and the first crossing of vref(dc). if the actual si gnal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value(see fig d.) although for slow slew rates the total setup time might be nega tive(i.e. a valid input signal wi ll not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is stil l required to complete the transition and reach vih/il(ac). for slew rate in between the values li sted in table x, the derating valued may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h 2.01254512545+125+45------------ 1.583218321+83+219533---------- 1.000000012122424 -------- 0.9---11-14-11-141-213102522------ 0.8-----25-31-13-19-1-71152317---- 0.7-----43-54-31-42-42-19-7-85-6176-- 0.6-----67-83---43-59-31-47-19-35-7-235-11 0.5-----110-125-----74-89-62-77-50-65-38-53 0.4-----175-188-------127-140-115-128-103-116 dq slew rate v/ns dqs, dqs differential slew rate tds, tdh derating values(all units in 'ps', note 1 applies to entire table) 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 0.8 v/ns
rev. 0.2 /dec 2006 28 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp fig. a illustration of no minal slew rate for tis,tds ck,dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf delta tr v ref to ac region nominal slew rate nominal slew rate t is , t ds v ref (dc)-v il (ac)max setup slew rate falling signal = delta tf v ih (ac)min-v ref (dc) setup slew rate rising signal = delta tr t ih , t dh t is , t ds t ih , t dh ck, dqs
rev. 0.2 /dec 2006 29 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp fig. -b illustration of tangent line for tis,tds ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf delta tr v ref to ac region tangent line tangent line t is , t ds ck, dqs nomial line nominal line delta tr tangent line[v ih (ac)min-v ref (dc)] setup slew rate rising signal = tangent line[v ref (dc)-v il (ac)max] setup slew rate falling signal = delta tf t ih , t dh t is , t ds t ih , t dh
rev. 0.2 /dec 2006 30 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp fig. -c illustration of nominal line for tih, tdh ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tr nominal slew rate nominal slew rate t is , t ds v ref (dc)-v il (dc)max hold slew rate rising signal = delta tr v ih (dc)min - v ref (dc) hold slew rate falling signal = delta tf dc to v ref region delta tf ck, dqs t ih , t dh t is , t ds t ih , t dh
rev. 0.2 /dec 2006 31 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp fig. -d illustration of tangent line for tih , tdh ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf tangent line tangent line t is , t ds ck, dqs nominal line dc to v ref region nominal line delta tr tangent line[v ih (ac)min-v ref (dc)] hold slew rate falling signal = delta tf tangent line[v ref (dc)-v il (ac)max] hold slew rate rising signal = delta tr t ih , t dh t is , t ds t ih , t dh
rev. 0.2 /dec 2006 32 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 9. tis and tih (input setup and hold) derating 1) for all input signals the total tis(setup time) and ti h(hold) time) required is calculated by adding the datasheet value to the derating value listed in above table. setup(tis) nominal slew rate for a ri sing signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)min. setup(tis) nomina l slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v il (ac)max. if the actual signal is always earlier than the nominal slew rate for line between shaded ?v ref (dc) to ac region?, use nominal slew rate for derating value(see fig a.) if the actual sign al is later than the nominal slew rate line anywhere between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see fig b.) hold(tih) nominal slew rate for a risi ng signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of v ref (dc). hold(tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc). if the actual ???? is always later than the nominal slew rate line between shaded ?dc to v ref (dc) region?, use nominal slew rate for derating value(see fig.c) if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref (dc) level is used for derating value(see fig d.) although for slow rates the total setup time might be negative(i.e. a valid input si gnal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input signal is still requir ed to complete the transi- tion and reach v ih/il (ac). for slew rates in between the values listed in table, th e derating values may obtained by linear interpolation. these values are typically not subject to production te st. they are verified by de sign and characterization. tis tih tis tih tis tih uni ts notes 4.0 +187 +94 tbd tbd tbd tbd ps 1 3.5 +179 +89 tbd tbd tbd tbd ps 1 3.0 +167 +83 tbd tbd tbd tbd ps 1 2.5 +150 +75 tbd tbd tbd tbd ps 1 2.0 +125 +45 tbd tbd tbd tbd ps 1 1.5 +83 +21 tbd tbd tbd tbd ps 1 1.0+0 0 tbdtbdtbdtbd ps 1 0.9 -11 -14 tbd tbd tbd tbd ps 1 0.8 -25 -31 tbd tbd tbd tbd ps 1 0.7 -43 -54 tbd tbd tbd tbd ps 1 0.6 -67 -83 tbd tbd tbd tbd ps 1 0.5 -100 -125 tbd tbd tbd tbd ps 1 0.4 -150 -188 tbd tbd tbd tbd ps 1 0.3 -223 -292 tbd tbd tbd tbd ps 1 0.25 -250 -375 tbd tbd tbd tbd ps 1 0.2 -500 -500 tbd tbd tbd tbd ps 1 0.15 -750 -708 tbd tbd tbd tbd ps 1 0.1 -1250 -1125 tbd tbd tbd tbd ps 1 tis, tih der ating values command / address slew rate(v/ns) 2.0 v/ns ck, ck differential slew rate 1.5 v/ns 1.0 v/ns
rev. 0.2 /dec 2006 33 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 10. the maximum limit for this parame ter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. min ( t cl, t ch) refers to the smaller of the actu al clock low time and the actual clock high time as provided to the device (i.e. this value can be greater th an the minimum specification limits for t cl and t ch). for example, t cl and t ch are = 50% of the period, less the half period jitter ( t jit(hp)) of the clock source, and less the half period jitter due to crosstalk ( t jit(crosstalk)) into the clock traces. 12. t qh = t hp ? t qhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or clock low ( tch, tcl). tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tdqsq: consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output sl ew rate mismatch between dqs/ dqs and associated dq in any given cycle. 14. t dal = (nwr) + ( trp/tck): for each of the terms above, if not already an integer, round to the next highest integer. tck refers to the application clock period. nwr refers to the t wr parameter stored in the mrs. example: for ddr533 at t ck = 3.75 ns with t wr pr ogrammed to 4 clocks. tdal = 4 + (15 ns / 3.75 ns) clocks =4 +(4)clocks=8clocks. 15. the clock frequency is allowed to change during self?refresh mode or pr echarge power-down mode. in case of clock frequency change during precharg e power-down, a specific procedure is required as described in section 2.9. 16. odt turn on time min is when the device leaves high impedance and odt resist ance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from taond. 17. odt turn off time min is when the de vice starts to turn off odt resistance. odt turn off time max is when the bus is in hi gh impedance. both ar e measured from taofd. 18. thz and tlz transitions occur in the same access time as valid data transitions. thesed parameters are referenced to a specific voltage level which specifies wh en the device output is no longer driving(thz), or begins driving (tlz). below figure shows a method to calculate the point when device is no longer driving (thz), or begins driving (tlz) by me asuring the signal at two different voltages. the actual voltage measure- ment points are not critical as long as the calculation is consistenet.
rev. 0.2 /dec 2006 34 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp 19. trpst end point and trpre begin point are not referenc ed to a specific voltage level but specify when the device output is no longer driving (trpst), or begins driving (trpre). below figure shows a method to calcu- late these points when the device is no longer driving (trpst), or begins driving (trpre). below figure shows a method to calculate these points when the device is no longer driving (trpst), or begins driving (trpre) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. 20. input waveform timing with differential data stro be enabled mr[bit10] =0, is referenced from the input signal crossing at the v ih (ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the v il (ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. 21. input waveform timing with differential data stro be enabled mr[bit10]=0, is referenced from the input signal crossing at the v ih (dc) level to the differential data stro be crosspoint for a rising signal and v il (dc) to the differential data strobe cr osspoint for a falling signal applied to the device under test. 22. input waveform timing is referenced from the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal appl ied to the device under test. 23. input waveform timing is referenced from the input signal crossing at the v il (dc) level for a rising signal and v ih (dc) for a falling signal appl ied to the device under test. dqs v ddq v ih(ac) min v ih(dc) min tdh tds dqs v ref (dc) v ss v il(dc) max v il(ac) max tdh tds differential input waveform timing thz , trpst end point = 2*t1-t2 tlz , trpre begin point = 2*t1-t2 voh + xmv voh + 2xmv vol + 1xmv vol + 2xmv thz trpst end point vtt + 2xmv vtt + xmv vtt -xmv vtt - 2xmv thz trpre begin point
rev. 0.2 /dec 2006 35 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp
rev. 0.2 /dec 2006 36 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp package dimension(x4,x8) 60ball fine pitch ball grid array outline 5. package dimensions note: all dimensions are in millimeters. < top view> 8.00 0.10 11.40 0.10 a1 ball mark 1.10 0.10 0.34 0.05 0.15 0.05 2-r0.13max < side view> 0.80 a1 ball mark 1.60 1.60 60x 0.45 0.05 < bottom view> 9 8 7 321 0.80 x 8 = 6.40 2.10 0.10 0.80 a b c d e f g h j k l
rev. 0.2 /dec 2006 37 hy5ps1g431c(l)fp hy5ps1g831c(l)fp hy5ps1g1631c(l)fp package dimension(x16) 84ball fine pitch ball grid array outline 0.80 a1 ball mark 1.60 1.60 84x 0.45 0.05 < bottom view> 987 321 0.80 x 8 = 6.40 2.10 0.10 0.80 a b c d e f g h j k l m n p r note: all dimensions are in millimeters. < top view> 8.00 0.10 13.00 0.10 a1 ball mark 0.15 0.05 2-r0.13max < side view> 1.10 0.10 0.34 0.05

▲Up To Search▲

Price & Availability of HY5PS1G831CFP-Y5

	To Download HY5PS1G831CFP-Y5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .